New ScanWorks shows versatility of boundary scan
The IEEE 1149.1 Boundary Scan Standard was originally developed almost a decade ago as a fundamental communications methodology for chips, circuit boards, subassemblies and systems. The first purpose to which this methodology was first applied was static structural interconnect testing.
ScanWorks version 3.5 represents the emergence of the next phase of boundary scan’s development. An embedded communications capability like boundary scan can be a bonanza in terms of the benefits it brings to developers, manufacturers and users.
The new ScanWorks brings together three new technologies that depend upon the communications facilities of 1149.1 boundary scan. In addition, several new features have been included in ScanWorks to add to its functionality.
The new technologies that have been integrated into the ScanWorks environment in version 3.5 are:
- IEEE 1149.6 Boundary Scan Standard for Advanced Digital Networks – This brings at-speed testing of AC-coupled buses like Gigabit Ethernet, Fibre Channel, LVDS and others to ScanWorks. For an article in this issue of Connect on “dot-6,” click here.
- ScanWorks Extended JTAG Coverage combines the test and programming capabilities of ScanWorks with the functional test capabilities of microprocessor emulation from International Test Technologies’ µMaster products. For an article in this issue of Connect, click here.
- IEEE 1532 Concurrent In-System (on-board) Configuration adds to ScanWorks the ability to simultaneously program multiple programmable logic devices (PLD) and field programmable gate arrays (FPGA) from various vendors. More on this new capability below.
Besides these new technologies, the functionality of ScanWorks has been enhanced in several significant areas. These include:
- Comprehensive Fault Coverage Report
- Scan Path Discovery Assistant
- Automated description of multiple scan paths
IEEE 1532 Concurrent In-System Configuration
With the integration of IEEE 1532 capabilities, ScanWorks is able to perform on-board programming of multiple PLDs and FPGAs from different vendors at the same time. Typically, the programming time for multiple devices will be dictated by the device that takes the longest to program.
The 1532 standard defines an internal register structure that is accessible by the 1149.1 communication infrastructure. The 1532 on-board configuration process is described by standard BSDL files. The standard also defines BSDL syntax for defining device-specific programming algorithms and a data file format that is read by a programming tool. The tool, in this case ScanWorks, can then program, erase, verify and perform other operations on PLDs and FPGAs. The device-specific BSDL files are supplied by the device vendor.
New PLDs and FPGAs that comply with the 1532 standard are supported by ScanWorks as soon as they are available. The following table shows the 1532 devices that are currently available from several different vendors. |
