CONNECT NEWSLETTER

asset-intertech.com

OBSERVATIONS

Clearing the air on
multiple scan paths
by Dave Bonnett
Technical Marketing Manager

Multiple scan paths on a design is sometimes unavoidable even though a single scan path would make it simpler to generate boundary-scan tests and provide better test coverage. Still, there are some good reasons and some not-so-good reasons for designs with multiple scan paths. Whatever the reason, ScanWorks has the capabilities and the flexibility to simplify the handling of multiple scan paths.

Making sure multiple scan paths are needed

Some designers assume they need multiple scan paths when, in fact, they don’t. There was a time when certain components and their vendor-supplied tools needed a separate scan path. CPU emulation tools, for instance, often required that the CPU be the only device on the scan path. This situation is changing now, as emulation tool vendors such as WindRiver support other devices besides the CPU on the scan path.

Perhaps the initial limitation of programming tools for programmable logic devices (PLDs) has led some designers to assume that PLDs still have to be on separate scan paths if vendor-supplied tools are being used. Fortunately, this assumption is no longer true. All PLD vendor tools can now find their way through other devices on the scan path. In fact, the IEEE 1532 In-System Configuration (ISC) standard was defined so that PLDs from multiple vendors on the same scan path can be programmed simultaneously.

Designers sometimes lack confidence in the JTAG capabilities of a certain device and, as a result, place it on a separate scan path. They fear that if the device doesn’t perform properly, it would limit boundary-scan access to other devices on the same path. Instead of designing in a second or third scan path dedicated to questionable devices, a better solution would be to design in bypass jumpers on prototype designs. If needed, the jumpers could exclude the questionable device or devices from the scan path during development and debug. Later, when the design moves into final production, the jumpers could be eliminated.

Another misconception of some designers stems from the fact that the length of a scan path affects the time it takes to program flash memory devices on-board. As a consequence, some designs include one path dedicated exclusively to programming and another path for test or other operations. Instead, a single path could be used for both without a significant effect on programming times. During a programming operation, devices on the single scan path not used for flash programming could be placed in the BYPASS mode and only one bit per additional device would be added to the chain, resulting in mere milliseconds of additional programming time, not seconds or minutes.

Of course, there are several good reasons for including multiple scan paths in a design. One, for example, involves testing several boards in a multi-board system. Testing multiple boards at once is sometimes particularly useful when stress or burn-in tests are being performed on several boards in an environmental chamber.

If a single boundary-scan test access port (TAP) is not available off of the system’s backplane, then each board must provide access to one or more TAPs, depending upon how many separate scan paths are present on each board. Boundary scan test systems like ScanWorks treat this situation in much the same way that they treat a single board with multiple scan paths. ScanWorks supports the use of scan path management devices to switch access among the scan paths if they are included in the board or system design. (For more information on ScanWorks’ support for scan path management devices, click here, or just keep reading.)

Another good reason for multiple scan paths is to reduce test times in a volume manufacturing environment by testing multiple identical boards at once. ScanWorks manages this situation by applying the same tests to all boards as part of one test operation. Each action is automatically applied either sequentially or simultaneously, depending on the type of test action. Serial numbers can be tracked for each board being tested, and separate test results are logged for each board. If an action for one board fails, testing on it stops but continues on all other boards unless the action fails on the other boards as well.

ASSET’s ScanWorks system features full hardware and software support for multiple scan path testing and programming. In addition, ad hoc or customized scan path management schemes are also possible.

ScanWorks’ Hardware Support for Multiple Scan Paths

ScanWorks has several hardware options that will interface to multiple scan paths. These include the PCI-400 hardware which supports four scan paths per interface pod, the PCI-100 or PXI-100 controller cards in combination with the Four TAP Buffer/Pod, or combinations of multiple PCI-400, PCI-100 or PXI-100 cards and pods.

• PCI-400 Hardware

ScanWorks’ PCI-400 multiple scan path interface hardware is very flexible and powerful. The PCI-400 Hardware Kit includes a PCI Multitap Controller Card, a Four-Port Boundary Scan Interface Pod and cables for connecting the controller card to the pod and the pod to the unit under test (UUT). With the PCI-400 hardware, ScanWorks can be connected to four independent scan paths. The four scan paths can be accessed individually or the paths can be combined by connecting them together to form one scan path. ScanWorks can connect to more than four scan paths by adding a second pod to a controller card. As many as three PCI Multitap Controller Cards can be installed in one PC-based ScanWorks station for a maximum of 24 scan paths. (4 TAPS/pod * 2 pods/card * 3 cards/PC = 24 TAPS/PC)

The PCI-400 hardware has a maximum test clock (TCK) frequency of 50 MHz. In addition, for most test actions the four TAPS on a pod can be logically combined as one scan path. This is helpful in certain situations. For example, it can improve the test coverage on a board that has more than one scan path. PCI-400 hardware also supports gang programming operations where flash programming data can be broadcast simultaneously to all four TAPS on one pod (broadcast mode). With the PCI-400 subsystem, the voltage of each TAP as well as its termination can be controlled through software. Each TAP is independent of the others. The PCI-400 subsystem also supports 20 discrete IO (DIO) non-boundary-scan signals.

Access to multiple scan paths connected with PCI-400 hardware is dynamically controlled by ScanWorks software. (Click here to read about ScanWorks software support for multiple scan paths or simply keep reading.)

• PCI-100 or PXI-100 with Four TAP Buffer/Pod

ScanWorks’ PCI-100 and PXI-100 hardware offer a great deal of flexibility at a low cost. When configured with the Single-Port Pod, a single scan path is connected to ScanWorks, but when the PCI-100 or PXI-100 is connected to the Four TAP Buffer/Pod, as many as four scan paths can be linked to ScanWorks. When this is the case, access to the multiple scan paths can be controlled either statically or dynamically. Static switches on the Four TAP Buffer/Pod will select the active scan path or the DIO signals can be used to dynamically determine the active path. The voltage for each scan path can also be set statically or dynamically at 1.8V, 2.5V, 3.3V, or 5V. As many as eight PCI-100 or PXI-100 controller cards can be installed in a ScanWorks PC, for a total of 32 scan paths. (8 cards/PC * 4 TAPS/pod/card = 32 TAPS/PC)

Software support for the PCI-100 and PXI-100 is well suited for test scenarios that are fairly stable.

ScanWorks’ Software for Multiple Scan Paths

ScanWorks’ methods for describing and controlling multiple scan paths are extremely flexible and automated. Generally, ScanWorks defines one printed circuit board (PCB) as a design. A design may contain descriptions for more than one scan path, but only one scan path can be active at a time. The active scan path can be a single scan chain or several scan chains can be combined in one scan path. The proper hardware interfaces are needed to connect ScanWorks to one or several scan paths. (See hardware information above.)

Each scan path described in a design is assigned a set of TAP signals that are identified by a channel (pod) number and a TAP number. User assigned identifiers for each channel help the user ensure that the TAP signals are physically connected to the correct scan path.

If a design has more than one scan path, the user specifies which scan path or which combination of scan paths will be active for each test or programming action. When an action is applied, it will automatically activate the scan path configuration it has defined. With PCI-400 hardware, as many as four scan paths can be connected to a single pod. All four scan paths can be active at once for certain actions because ScanWorks automatically connects them to form one scan path for test generation and application. With the PCI-100 or PXI-100 hardware, multiple scan paths must be configured manually.

If more than one UUT is being tested simultaneously, the same scan path description can be assigned to more than one set of TAP signals. The active TAP signals can be selected when tests are applied, enabling the testing of multiple boards in one operation. If TAP test signals for more than one board are active, tests are applied to each board sequentially. However, flash programming is automatically applied to multiple boards simultaneously in broadcast mode, significantly reducing the total programming time.

Although the PCI-400 hardware is automatically configured by ScanWorks, the PCI-100 and PXI-100 Hardware Cards with Four TAP Buffer/Pods must be configured manually because ScanWorks software supports one scan path per pod. Whereas each PCI-100 or PXI-100 hardware card and Four TAP Buffer/Pod are mapped as a single scan path, the actual path could be any one of the four scan paths connected to the Four TAP Buffer/Pod or it could be a combination of the four scan paths connected to the Four TAP Buffer/Pod. In any case, the configuration of the scan path must be described as one scan path in the design definition that ScanWorks is currently working with.

If more than one PCI-100 or PXI-100 card is installed in a PC-based ScanWorks station, each card can be assigned to the same scan path for testing multiple UUTs simultaneously, or each controller card can be assigned to a different scan path in another design. If multiple UUTs are being tested, the user selects which Scan Paths will be active during the test. If several scan paths are being tested as part of a test sequence, a scan path is active only when it has been selected in the design’s description. ScanWorks’ application programming interfaces (APIs) can be used to create a sequence of tests that are applied to different UUTs sequentially, automatically activating the correct set of TAP signals for each UUT.

Scan Path Management Devices

Some designs include scan path management devices to control access to multiple scan paths. Each of these devices has as its input a primary scan path, but, depending upon the device, several additional secondary scan paths also can be controlled. The management device activates the secondary scan paths through proprietary command protocols that are sent using TAP signals.

ScanWorks supports most of the commercially available scan path management devices. Models of these management devices and example files for controlling secondary scan paths are included with ScanWorks. In a typical ScanWorks action, the active scan paths are set as a precondition to the action. An action is developed for a particular configuration of the scan path. To ensure that the scan path is correctly configured, the commands which configure the scan path are automatically executed each time the action is run.

The scan path management devices supported by ScanWorks include:

Texas Instruments

• Addressable Scan Port (ASP) - sn74abt8996
• Linking Addressable Scan Port (LASP) - sn74lvt8986
• Scan Path Linker (SPL) - sn74act8997

For more information on these devices, click here.

National Semiconductor

• Multidrop and Addressable JTAG Port SCANPSC110f SCAN Bridge
• Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG Port) - SCANSTA110
• 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer - SCANSTA112

For more information on these devices, click here.

Firecron

• Gateway Device - JTS03
• Gateway Device - JTS06
• Available from Alliance Semiconductor

For more information no these devices, click here.

Lattice Semiconductor

• Multiple Boundary Scan Port Linker – LSC BSCAN-2

For more information on this device, click here.

Shortening Time-to-Test

With the increasing complexity of many printed circuit boards today, effectively handling multiple scan paths is imperative. But ScanWorks’ multi-scan path capabilities do not stop with simple support. The many automation features that have been built into ScanWorks make managing multiple scan paths intuitive and easy. As a result, the time it takes to develop a test, or time-to-test, is shortened significantly.