 New
boundary-scan standard (IEEE Std 1149.6) will test high-speed
interconnects
by Adam Ley
Chief Technologist
Since the passage of IEEE Std 1149.1
more than a decade ago, the boundary-scan standards
have evolved along the same lines as the electronics
industry. As new end-user technologies and product platforms
have been introduced into the marketplace, boundary-scan
standards have been modified and extended to meet the
needs of test engineers and electronics manufacturers.
The most recent revisions are embodied
in a new standard and designated IEEE Std 1149.6. This
boundary-scan standard has become necessary because
of the growing popularity of high-speed serial interconnects
for chip-to-chip communications and communications between
printed circuit boards. The high speeds of these interconnects
(extending to 10Gbps and beyond) and the sensitive nature
of the chip drivers and receivers demand greater use
of well-known but non-conventional board net topologies.
The most notable of these are AC coupling and differential
signaling.
At the time that IEEE Std 1149.1 originally
was developed, chip-to-chip interconnects were mostly
wide, parallel data paths. The static nature of conventional
boundary-scan tests was adequately suited for these
relatively low-speed interconnects. The new IEEE Std
1149.6 builds on the original standard, as well as IEEE
Std 1149.4 for the testing of interconnections between
analog components, but adds certain functions and capabilities
that are needed to test the finely-tuned high-speed
serial interconnects that are appearing on many printed
circuit boards (PCBs) today. Boards being developed
for some segments of the electronics industry, such
as high-speed fiber-optic switching equipment, already
feature hundreds, if not thousands, of these high-speed
serial links.
The trouble with high-speed
serial interconnects
High-speed serial, peer-to-peer communications
techniques on PCBs typically employ one or both of two
net topologies that are addressed specifically in IEEE
Std 1149.6: AC coupling and differential signaling.
With AC coupling, some sort of static
DC-blocking device, such as a capacitor, is interposed
between driver and receiver. As a result, driver and
receiver can have different steady state voltages and
their common mode ranges need not overlap. Thus, a higher
degree of cross-vendor, cross-component interoperability,
and hence, a higher degree of interconnect reliability,
is more readily achieved.
In differential signaling, two drivers
are paired in such a way that the two logical wires
that span the interconnection are always driven to complementary
voltages. The receivers, in turn, discern the logical
state of the interconnection according to the polarity
of the difference between the voltages on the two wires.
A difference that is nominally positive determines a
logic 1, while a difference that is nominally negative
determines a logic 0. As a result, all common-mode noise
is rejected. Thus, a higher degree of noise immunity,
and hence, a higher degree of interconnect reliability,
is more readily achieved.
Fundamentally, both of these net topologies
effectively block static DC test methodologies, requiring
dynamic AC stimulus for adequate test coverage. Quite
simply, because of the static DC nature of IEEE Std
1149.1 boundary-scan testing, its techniques cannot
test such net topologies.
Further, while differential interconnects
can be made static and DC-testable, to do so requires
that the two wires be treated discretely. In other words,
if IEEE Std 1149.1 is to be brought to bear, two test
drivers and two test receivers must be deployed for
each differential pair. Thus, boundary-scan cells would
have to be inserted effectively between the differential
drivers and receivers and the respective chip pads,
but this has often created an unacceptable degradation
in performance.
IEEE Std 1149.6 to the rescue
When a typical static DC-coupled interconnection
is tested with an IEEE Std 1149.1 test system, a boundary-scan
cell drives either a logic 0 or logic 1, as represented
by a low or high voltage, respectively. But, in either
case, there is a significant period of time for the
signal to make its transition and for the transition
to be monitored at a receiving boundary-scan cell. Because
high-speed dynamic AC-coupled nets do not afford the
same period of time to sense signal transitions before
the driven DC level decays, an AC stimulus must be generated
and sampled dynamically in order to test the interconnection
between driver and receiver.
IEEE Std 1149.6 does this by encoding
logic 0 and logic 1 values driven from a boundary-scan
cell as a pulse which then propagates through the DC-blocking
device in the high-speed serial interconnect. A receiving
boundary-scan cell, in turn, monitors the interconnection
for a pulse edge, interpreting a rising edge as a one
and a falling edge as a zero. In this way, a static
signal is encoded into a dynamic stimulus by the driver
and a dynamic response is converted into a static signal
by the receiver. A complete explanation is beyond the
scope of this introductory article. Further discussion
is available in the working group archives at http://grouper.ieee.org/groups/1149/6/
In this way, the IEEE Std 1149.6 methodology
results in tests for high-speed interconnections that
originate as static stimulus and result in static response
just as IEEE Std 1149.1 does. Thus, tests generated
by IEEE Std 1149.1 boundary-scan systems can be used
to test the interconnections between IEEE Std 1149.6-complaint
chips. In fact, when IEEE Std 1149.6-compliant silicon
becomes more prevalent and the demand for IEEE Std 1149.6
boundary-scan test increases, the inclusion of IEEE
Std 1149.6 testing into the leading boundary-scan systems
like ScanWorks will be transparent to users and IEEE
Std 1149.6 tests will be generated automatically, just
as IEEE Std 1149.1 tests are generated today. |
