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Success Stories

Hewlett Packard impressed by ease-of-use of ScanWorks® JTAG system

"I'm an engineer but I'm like everybody else: If you show me a text-based interface, you're going to lose me," said Mike D'Amico, Manufacturing Test Engineer for Hewlett Packard Corporation's LaserJet Printer Division. "The graphical user interface (GUI) for ASSET's ScanWorks JTAG system is great. It helps tremendously because I can more intuitively understand the system; it has to be straightforward to use since none of our people can be dedicated entirely to JTAG test development at this time. Since we just don't know a whole lot about boundary scan (IEEE 1149.1, 2001/JTAG), the simplicity of the interface is very important to us."

For the time being, HP's LaserJet Printer Division is using ScanWorks as a design debug tool to troubleshoot prototype printed circuit assemblies (PCAs) via JTAG. But, over the longer term, D'Amico's group plans to implement the integrated ScanWorks for the Agilent 3070 in-circuit test solution.

Integrating with ICT

"Right now, the simplicity of ScanWorks helps us to exercise our PCAs early in the design process so we can identify any problems and correct them quickly. The people in our design lab are very sold on the value of ScanWorks. Eventually, we want to use the integrated ScanWorks for the 3070 solution because our PCA’s are being populated with more and more ball grid arrays with 400 to 800 pins as well as other types of fine pitch packages. Without ScanWorks, we just can't do a high level of logical debug on a PCA that has these types of devices."

Involving Design

D'Amico is hoping that more of the design engineers at HP's LaserJet Printer Division will come to realize the value of boundary scan and ScanWorks. "If we can get the design group interested in boundary scan, then they can design it into more of the application specific integrated circuits (ASIC’s) they are developing," D'Amico explained. "And with boundary scan built into our ASIC’s, we could do a lot more built-in-self-test (BIST)."

Currently, when an ASIC is developed, ASSET's services organization, Ensure Design for Test (EDFT), verifies the accuracy of the device's boundary scan description language (BSDL) file. Effective boundary scan tests can not be developed without an accurate BSDL file for the devices on a scan path.

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