IEEE P1838

Test Access Architecture for Three-Dimensional
Stacked Integrated Circuits


Scope: Architecture and methodology for access to embedded test and debug features of individual and collective 3D Stacked-Die made with Through-Silicon Vias (TSV's). These test features must be accessed before stacking to become Known-Good Die; may be accessed during stacking; and must be accessed after stacking and packaging. In
addition, some test features may be proposed to address the added problems of a 3D stack such as TSV verification. It is expected that P1838 will leverage other IEEE Standards such as 1149.1, 1500, and P1687.

Up and down the elevator

Once adopted, 1838 will make it possible to run tests between phases of die-stack assembly.  Structural and functional tests for the entire stack will be accessible through a package-level TAP.  Access that may be impossible with physical probing can then be achieved using software tools, such as the ScanWorks Platform for Embedded Instrumentation.
IEEE Site:  http://grouper.ieee.org/groups/3Dtest/

ASSET Participant: Al Crouch

Current Status: Discussing 1500 signals.  The chairman has taken ownership of the document.

Upcoming Events of Interest:
IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST)
3D-TEST 2012: November 8+9, 2012 - Anaheim, California, USA (in conjunction with ITC)

Articles of Interest:
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