logo

IEEE 1581

Static Component Interconnection
Test Protocol and Architecture

 

Scope: IEEE 1581 defines a low-cost method for testing the interconnection of discrete, complex memory IC’s where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1) is not feasible. This standard describes the implementation rules for the test
logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.

Memory Interconnections

Structural test of memory device interconnections is time consuming and is becoming impractical as new memory technologies emerge.  JEDEC has begun adopting IEEE 1581 as a requirement for some new memory devices in order to solve these problems.  The ScanWorks Platform supports IEEE 1581 by way of the Component Action.
IEEE Site: http://grouper.ieee.org/groups/1581/
JEDEC Site: http://www.jedec.org

ASSET Participant: Adam Ley

Current Status: Approved in March 2011

Upcoming Events of Interest:

Articles of Interest:


Return to Standards List
 

CPU & FPGA Support

ScanWorks supports Intel®, ARM®, Freescale™,
& other CPUs; Altera® and Xilinx® FPGAs.

See the full range