Scope: IEEE 1149.7 describes circuitry that may be added to an IC to provide access to on-chip TAPs specified by IEEE 1149.1-2001, while adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0–T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system.