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IEEE 1149.7

Reduced-pin & Enhanced-functionality Test Access Port
& Boundary-Scan Architecture

 

Scope: IEEE 1149.7 describes circuitry that may be added to an IC to provide access to on-chip TAPs specified by IEEE 1149.1-2001, while adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0–T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system.
Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.

IEEE 1149.7 offers lower power, fewer pins, more functionality....

The standard specifies enhancements that may better support designs with system-on-chip or multi-die packages.  It also specifies features for TAP power management, reduction in pins dedicated for test, and enhancements for software debug. The ScanWorks platform supports 1149.7.
IEEE Site: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5412864

ASSET Participant: Adam Ley

Current Status: Approved December 9, 2009

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