IEEE 1149.6

A Boundary-Scan Standard for Advanced Digital Networks


Scope: This project will define an extension to IEEE Std. 1149.1-2001 to standardize the boundary scan structures and methods required to ensure simple, robust, and minimally intrusive boundary scan testing of advanced digital networks not adequately addressed by existing standards, especially those networks that are AC-coupled, differential, or both, in parallel with IEEE Std. 1149.1 testing of conventional digital networks and in conjunction with IEEE Std. 1149.4 testing of
conventional analog networks.   This project will be complementary to IEEE 1149.4, specifically targeting parallel testing of advanced digital networks while IEEE1149.4 focuses on serial testing of more traditional analog networks.  This project will also specify any software or BSDL extensions to IEEE Std. 1149.1-2001 which are required to support this new I/O test structure.

a.k.a AC EXTEST or DOT 6

Existing boundary scan test standards (IEEE Std. 1149.1-2001, IEEE Std. 1149.4-1999) did not fully address some of the increasingly common, newer digital network topologies, such as AC-coupled differential interconnections on very high speed (1+ GBps) digital data paths.  IEEE Std. 1149.1 structures and methods are intended to test static (that is, DC-coupled), single ended networks.  It is unable to test dynamic (that is, AC-coupled) digital networks, since AC-coupling blocks static signals. Differential networks are also inadequately tested by the current IEEE Std. 1149.1-2001, which requires either the insertion of boundary cells between the differential driver or receiver and the chip pads (this often creates an unacceptable performance degradation), or insertion of single boundary cells before the differential driver and after the differential receiver (this reduces controllability and observability to the point that many board assembly defects cannot be detected).  IEEE Std. 1149.4-1999 structures and methods are intended for testing analog networks, and in most cases are not able to test these newer digital networks as well. Specifically, IEEE Std. 1149.4-1999 provides the opportunity to inject dynamic (time varying) or analog signals for test, but these structures intended for analog testing are often too intrusive (too high an impact on performance and pin count) for high speed chip designs, and require additional resources and test application time not otherwise required for testing digital circuits. Finally, very high-speed logic imposes new restrictions on test structures that were not considered in IEEE Std. 1149.1.  This project defined standard, robust, and minimally intrusive test structures and methods that provide greater detection and diagnostic capability than existing structures and methods for these classes of digital networks.  The project addressed the physical interface between components, the protocol for sending test data between components and the boundary scan interface.  The project also addressed software and BSDL changes that were required to support the standard.

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