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JTAG (IEEE 1149.x)

In general, JTAG refers to the technology described in the IEEE 1149.x family of boundary-scan standards. The base standard, IEEE 1149.1, is often referred to as JTAG after the Joint Test Action Group, which initiated the development of the specification before it was adopted by the IEEE.

 
In recent years, the term JTAG has been closely associated with the port on a processor that implements the IEEE 1149.1 boundary scan interface or Test Access Port (TAP). This interface is often simply called the JTAG port on the device. It typically functions as a debug port and can be used for a number of purposes, including structural board test, on-board programming of memory devices, the configuration of CPLDs and FPGAs, memory testing and others.

 

IEEE 1149.1 Test Access Port (TAP) and Boundary-Scan Architecture (JTAG)

The official name of the JTAG standard is the IEEE 1149.1 Test Access Port (TAP) and Boundary-Scan Architecture. It was developed during the 1990s as a non-intrusive board test technology in response to several developments in the industry which tended to preclude the use of intrusive, probe-based board test technologies, such as in-circuit test (ICT), flying probe and others. Ever since the development in the early 1990s of fine-pitch pins on chips and chip-scale packages such as ball grid arrays (BGA) which placed device pins underneath the silicon die, physical access for intrusive probes for board test purposes has been disappearing. Moreover, many circuit boards could not accommodate the test pads that had been essential to probe-based test technologies. Instead, JTAG or boundary-scan tests are applied to a circuit board through a connector and the four-wire TAP interface.

IEEE 1149.1 JTAG and Boundary Scan Tutorial - e-Book  IEEE 1149.1 JTAG and Boundary Scan Tutorial - e-Book

 

IEEE 1149.6 Boundary-Scan Standard for Advanced Digital Networks

Based on the groundwork laid by the IEEE 1149.1 boundary-scan standard, the IEEE 1149.6 specification defines test methodologies for high-speed buses in the one to 10 gigabits-per-second (Gbps) range that feature serial AC-coupled chip-to-chip interconnects and/or differential signaling, such as Gigabit Ethernet, Fibre Channel and others. Typically, IEEE 1149.1 boundary scan only tests the DC-coupled device networks on a circuit board.

 

IEEE 1149.7 Standard for Reduced-Pin and Enhanced Functionality Test Access Port (TAP) and Boundary-Scan Architecture

Ratified by the IEEE in 2009, the IEEE 1149.7 standard is backward compatible with the original IEEE 1149.1 standard, but this newer standard offers options for a smaller, two-wire interface and enhanced functionality. IEEE 1149.7 extends the test and debug capabilities of the IEEE 1149.1 TAP to complex devices like system-on-chip (SOC), system-in-package (SIP) and other multi-core or multi-die 3D devices.

 

IEEE 1532 Standard for Boundary-Scan-Based In-System Configuration of Programmable Devices

The IEEE 1532 standard uses the IEEE 1149.1 boundary scan standard as an underlying technology to define an open and standardized method for programming logic devices after they have been assembled onto a printed circuit board. The standard also specifies concurrent programming capabilities which allow more than one programmable device to be simultaneously configured in-system.

 
Information on these and other IEEE standards is available on the IEEE web site.

Other ScanWorks Technologies…

For information on any of the other technologies supported by the ScanWorks platform for embedded instruments, click on one of the following: 
The Evolution of Test
JTAG (IEEE 1149.x)
On-Chip Debug
SerDes BIST
Intel® IBIST
IJTAG (IEEE P1687 Internal JTAG) and other embedded instrumentation standards
 

CPU & FPGA Support

ScanWorks supports Intel®, ARM®, Freescale™,
& other CPUs; Altera® and Xilinx® FPGAs.

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