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ScanWorks IJTAG Test

ScanWorks IJTAG Test

Interact with your instruments

The ScanWorks® Internal JTAG (IJTAG) tools allow system-on-a-chip (SoC) designers, DFT engineers and validation engineers a new and simpler way to access, control and run any embedded instrument designed into chips. The ratified IEEE 1687 Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device defines a scaleable and reusable methodology to operate embedded instruments. ASSET was the first tool supplier with development tools available today for the early adopters of this important new technology.

Once instruments are connected to the on-chip IJTAG network, ScanWorks reads the IJTAG standard’s Interconnect Connectivity Language (ICL) and automatically knows where all the instruments in the chip are. Then ScanWorks uses the IJTAG standard’s other language, Procedural Description Language (PDL), to run the embedded instruments that have been selected to solve the problem at hand.

Currently, tools to control embedded instruments, if they exist at all, are usually proprietary to a certain technology. As a result, the engineer would need multiple tools and multiple access mechanisms, or he would have to develop his own tools. The IJTAG standard and ScanWorks IJTAG chip test and debug tools solve this mess.

Software - driven instruments

ScanWorks IJTAG Test tools are another non-intrusive validation, test or debug technology for the ScanWorks platform for embedded instruments. Semiconductor companies can use ScanWorks IJTAG tools to develop and/or process ICL and PDL content during first silicon bring-up to verify in situ access and operation of embedded instruments that are critical to the success of their customers board applications.  Once silicon ramps into production, the manufacturing flow of the chip can utilize the ScanWorks Platform to re-use the ICL and PDL content during QA gates as well as burn-in oven stimulus.

Once a chip leaves the semiconductor manufacturer and is designed into a circuit board, the board designer can re-use the same ScanWorks IJTAG tools, as well as the same ICL and PDL content for the embedded instruments, to validate, test and debug the board itself, should the board’s test strategy call for this and the embedded instruments possess the test capabilities needed. In addition, the semiconductor manufacturer can work with their customers to perform in situ fault diagnostics during board bring-up as well as board failures in the field.  These capabilities enable valuable synergy between an SoC supplier and its customer. When a difficult problem is found, the supplier and customer can use the same tools, work together and share data to solve product integration problems quickly.


Find out more about why both chip and board designers should use IJTAG (IEEE 1687).

IJTAG Test Development Software

The ScanWorks® IJTAG Test Development Software is an automated and extremely flexible methodology for accessing and controlling embedded instruments in system-on-a-chip (SoC) designs to help debug these very complex devices. To get started, ScanWorks simply reads-in the IJTAG Interconnect Connectivity Language (ICL) and Procedural Description Language (PDL) files. ScanWorks then displays all the instructions and functions that each instrument can perform. All the engineer does is drag and drop the sequence of events and tests he wants the instruments to perform. It’s that simple!

Once satisfied with the test program for a certain instrument, the developer just clicks Run and the instruments embedded in the SoC are automatically test the device.

Find out more about why both chip and board designers should use IJTAG (IEEE 1687).



  • Validate, test and debug complex SoCs within one environment using all the IJTAG instruments designed into the chip.
  • Accelerate debug and test times by running multiple instruments concurrently.
  • Validate instruments and perform tests right from the chip designer’s desk. No need to fight for precious and expensive IC ATE tester time.
  • Easily integrate into a load board to complement IC ATE.
  • Empower the SoC customer – the board designer – with the same tools that were used by the chip designer. Shorten the board designer’s board bring-up cycles by leveraging instruments embedded in the SoC. This adds even more value to the SoC.

IJTAG Test Manufacturing Software

SoC Developer:

ScanWorks IJTAG Test Manufacturing software can be used stand-alone or as a complement to IC ATE via a connection to the chip-under-test on a load board. Thus, IC ATE focuses on what it does best and IJTAG test capabilities are added at a very low cost.

SoC Customer doing Board Test:

The SoC user who is re-using some of a chip’s embedded instruments in manufacturing board test can add an IJTAG Test Manufacturing license to the other applications deployed on any ScanWorks platforms already performing manufacturing test. The IJTAG test applications complete the ScanWorks board test capabilities by covering issues concerning specific SoCs. In addition, when problems arise and boards must be diagnosed, another tool is available within the ScanWorks environment.

  • Re-use ScanWorks IJTAG test instruments that were employed during SoC test and board bring-up
  • Extend test coverage for SoCs by complementing IC ATE and for board test as another ScanWorks application
  • Utilize as a data collection instrument engine for characterization, failure analysis and yield analysis during the SoC process
  • Run any instrument on the IJTAG network in the chip with the built-in PDL engine

IJTAG Technology - IEEE 1687 Webinar


The new IEEE 1687 Internal JTAG (IJTAG) standard is changing the way the industry validates, tests and debugs chips and circuit boards. IJTAG-based methods are more cost-effective, more accurate, faster and less time-consuming for you than legacy probe-based technologies. IJTAG’s software-driven tests and validation routines are initiated from instruments embedded inside chips. Don’t miss the chance to learn how to tap into this useful IP.

Who Should Attend
  • DFx Engineers that need to insert the IJTAG networks and gain the benefits of accessing IP within the silicon
  • Board Designers that want to gain the benefit of enhanced board validation and test features accessed by IJTAG
  • Test Managers that want to improve their overall test process and resolve test challenges that cannot be addressed with current test technologies

NOTE: This event is a web presentation of similar events that were presented face-to-face in cities across US, Europe, and Asia in February, March, and April 2015, respectively.

What You Will Learn
  • Basic overview of the IEEE 1687 standard including its PDL and ICL languages
  • Overview of Mentor automation for integrating and validating 1687-compliant IP into an SOC
  • Overview of ASSET InterTech software for interacting with SOC 1687-compliant IP at the board and system level
About the Presenters

Presenter ImageAdam Ley
Chief Technologist, Non-intrusive Board Test and JTAG

Adam ensures that ASSET’s non-intrusive board test (NBT) methodologies comprise a best-in-class solution to meet the evolving need for improved coverage of board test in the face of ongoing erosion of physical access. Pursuant to ASSET’s strong support for standards, Adam is an active participant in IEEE 1149.1, having previously served terms as working group vice chair and as standard technical editor (for the 2001 revision), as well as in nearly all related standards, to include: 1149.4, 1149.5, 1149.6, 1149.7, 1149.8.1, 1500, 1532, 1581, P1149.1.1, P1149.10, iNEMI boundary-scan adoption, PICMG MicroTCA, and SJTAG (system JTAG). Adam’s experience prior to ASSET spanned over a decade at Texas Instruments, Sherman TX, where he had roles in application support for TI’s boundary-scan logic products and for test and characterization of new logic families. Adam earned the BSEE degree from Oklahoma State University, Stillwater OK, in 1986

Presenter ImageMartin Keim
Engineering Manager, Mentor Graphics

Dr. Martin Keim joined the Silicon Test Solutions group of Mentor Graphics in 2001, where he is currently Engineering Manager of the Memory Built-In Self-Test team. He is an active member of the IEEE 1687 working group and was editor of the sixth edition of the Microelectronics Failure Analysis Desk Reference Manual, responsible for the test and diagnosis chapters. For several years, Dr. Keim has worked on the organizing committee of the International Symposium for Testing and Failure Analysis, for which he will be General Chair in 2016. He holds several national and international patents and is author of many technical publications. He received a doctorate in Informatics from the Albert-Ludwigs University in Germany.


Hardware for ScanWorks

Hardware for ScanWorks

The ScanWorks platform for embedded instruments is supported by a wide variety of hardware controllers and accessories with which engineers can connect ScanWorks to their unit under test (UUT). Hardware is available for development, production and repair environments. The test platform required for ScanWorks is either a standard PC or a system with a built-in (embedded) JTAG controller.

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