ScanWorks® IJTAG Test

Control embedded instruments
Automate instrument access
Debug complex SoCs

Interact with your instruments

The ScanWorks Internal JTAG (IJTAG) tools allow system-on-a-chip (SoC) designers, DFT engineers and validation engineers a new and simpler way to access, control and run any embedded instrument designed into chips. The ratified the IEEE 1687 IJTAG standard enables easy access to run any functional type of IJTAG instrument. ASSET was the first tool supplier with development tools available today for the early adopters of this important new technology.

Once instruments are connected to the on-chip IJTAG network, ScanWorks reads the IJTAG standard’s Interconnect Connectivity Language (ICL) and automatically knows where all the instruments in the chip are. Then ScanWorks uses the IJTAG standard’s other language, Procedural Description Language (PDL), to run the embedded instruments that have been selected to solve the problem at hand.

Currently, tools to control embedded instruments, if they exist at all, are usually proprietary to a certain technology. As a result, the engineer would need multiple tools and multiple access mechanisms, or he would have to develop his own tools. The IJTAG standard and ScanWorks IJTAG chip test and debug tools solve this mess.

Software - driven instruments

ScanWorks IJTAG Test tools are another non-intrusive validation, test or debug technology for the ScanWorks platform for embedded instruments. Chip designers will first use ScanWorks IJTAG tools to validate instruments in silicon and later apply the instruments to validate the host chip, such as an SoC. Then, as manufacturing ramps up, ScanWorks IJTAG tools could complement a typical IC ATE production test flow.

Once a chip leaves the semiconductor manufacturer and is designed into a circuit board, the board designer can re-use the same ScanWorks IJTAG tools, as well as the embedded instruments, to validate, test and debug the board itself, should the board’s test strategy call for this and the embedded instruments possess the test capabilities needed. This process provides valuable synergy between an SoC supplier and its customer. When a difficult problem is found, the supplier and customer can use the same tools, work together and share data to solve any problem quickly.

IJTAG Test Software

ASSET provides its ScanWorks IJTAG validation and  test software in a variety of packages.

Development Software – The ScanWorks IJTAG Test Development software provides a robust environment to develop instrument test programs via an easy-to-use, drag-and-drop user interface. No code is written! ScanWorks IJTAG Test Development software automatically reads both of the IJTAG standard’s languages, ICL and PDL, so the environment for test development and debug is available immediately.
Manufacturing Software – As with all ScanWorks toolkits, rapid test development with ScanWorks IJTAG Test development software can be followed by an easy migration to manufacturing under the IJTAG Test Manufacturing software, which includes an IJTAG PDL engine to run tests as well as many other features.

Learn More

IJTAG Technical Workshop Series

This is a full day DFT seminar which includes morning and afternoon sessions and will be presented worldwide. There will be experts from both ASSET InterTech and Mentor Graphics at every location. You will have the opportunity to learn more from the experts at this free seminar.

More about the seminar

CPU & FPGA Support

ScanWorks supports Intel®, ARM®, Freescale™,
& other CPUs; Altera® and Xilinx® FPGAs.

See the full range