Most of the leading processor families from suppliers like Intel®, Freescale and others feature certain debug capabilities on-chip. This set of features can be utilized by external toolsets or testers to perform board-level validation, test and debug applications. How effectively a particular processor family’s on-chip debug features are applied will depend on which debug features are embedded in a particular chip and the capabilities of the external toolset which makes these capabilities available to engineers.
The on-chip debug features contained in a processor can be applied at various points in the life cycle of a circuit board, beginning with prototype board bring-up and continuing through device initialization, firmware development, at-speed functional and structural board test and later in the life cycle.
The on-chip debug feature set is accessed through a debug port on the processor. For example, Intel® calls its processor debug port the eXtended Debug Port (XDP) while Freescale™ refers to its debug port as NEXUS or the Common On-Chip Processor (COP). To apply a processor’s on-chip debug capabilities in board-level validation, test and debug applications, access to the device’s debug port must be provided on the circuit board. This allows the processor – the most powerful instrument on the board – to be deployed in test and measurement applications. A prime example of a board-level test and debug application that is able to take advantage of a processor’s on-chip debug features is processor-controlled test (PCT) which performs various at-speed functional and structural tests on boards via the processor’s debug port.
Certain design-for-test (DFT) requirements must be considered on circuit boards to fully utilize a processor’s on-chip debug features. Click here to consult with one of ASSET’s DFT experts who can guide you to the resources you need and offer their advice.
The following are several useful resources that chip suppliers have compiled regarding their on-chip debug facilities.
Download Intel’s “Debug Port Design Guide for UP/DP Systems”.
Download Intel’s “JTAG 101 IEEE 1149.x and Software Debug” white paper.
Download Freescale’s application note, “Power Architecture™ Demystified.”
Download Freescale’s application note, “MPC553x, MPC555x, and MPC556x Family Nexus Interface Connector.”
More information on using the Freescale Common On-Chip (COP) debug port.
More information on the ARM Debug Interface.
More information on ARM's Serial Wire Debug port.
Many of the Cavium embedded processors are based on 64-bit processor cores from Inagination, formally MIPS Technologies. Click here to find out more about MIPS64 Architecture.
Other ScanWorks Technologies…
For information on any of the other technologies supported by the ScanWorks platform for embedded instruments, click on one of the following:
The Evolution of Test
JTAG (IEEE 1149.x)
IJTAG (IEEE P1687 Internal JTAG) and other embedded instrumentation standards