Turn the chip inside out
Integrated circuits will only continue to get smaller and more complex. And with each new geometry shrink comes new difficulties in verifying, testing and characterizing the device. Different fault types, like parametric bridges, are manifested at smaller geometries and they can only be found with at-speed tests. And that means more time and more expensive instruments on automatic test equipment (ATE) where costs escalate by the fraction of a second. Plus testing complex system-on-a-chip (SoC) devices containing analog and digital blocks comes with an extreme premium cost on ATE systems where expensive instruments are needed to perform such tests.
The ScanWorks platform for embedded instruments enhances chip test and debug by taking advantage of instruments already embedded in the chips themselves and the new breakthrough standard, the IEEE P1687 Internal JTAG (IJTAG) standard for embedded instruments. Now chip manufacturers have an alternative to loading up ATE systems with additional and more expensive instruments, driving up chip test costs astronomically.
Inserting ScanWorks into the chip test process flow reduces the need for expensive ATE instruments and the time an IC spends on a costly ATE system. By tapping into the instruments already embedded in chips, ScanWorks achieves better test and diagnostic coverage while lowering the overall cost of chip test. In fact, ScanWorks could complement existing ATE chip test. ScanWorks FPGA-controlled test (FCT) could embed a chip tester into an FPGA on an ATE loadboard, reducing the need for expensive instruments and test time on the ATE system.
Find out how ScanWorks tests and debugs chips from the inside out, not the other way around.
Let us explain