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![]() ![]() The industry's first JTAG Design-for-Test (DFT) Labs have been established by ASSET InterTech in San Jose and London. The labs validate the JTAG (boundary scan or IEEE 1149.1) infrastructure in chip and printed circuit board designs.ASSET's DFT labs, which are meant for first-time users of boundary scan, are offering a FREE analysis of pre-prototype designs as well as FREE advice on how the design’s DFT infrastructure could be optimized. The labs' reports ensure that a chip or PCB design’s embedded JTAG infrastructure can be effectively used for standard JTAG structural testing and in-system programming, as well as advanced applications like the testing and design validation of high-speed AC-coupled serial buses (IEEE 1149.6), Intel® Interconnect Built-In Self-Test (IBIST), system-level remote JTAG testing, concurrent programming (IEEE 1532) and others. The DFT Labs' comprehensive test coverage reports describe the defect coverage present and recommend how DFT coverage might be optimized to improve yields and reduce cost. ASSET’s state-of-the-art JTAG tools are used to perform all of the labs' DFT reviews. PCB analyses are accomplished with ASSET’s DFT Analyzer™, a recent finalist in the International Engineering Consortium’s (IEC) prestigious DesignVision Awards and the only design tool that automatically validates the JTAG testability in board designs. The accuracy of a chip design’s Boundary-Scan Description Language (BSDL) files is validated syntactically and semantically with the ASSET/Agilent BSDL Validation Service and ScanWorks®, ASSET’s flagship JTAG test system. Other tools, such as International Test Technologies’ microMaster for functional test, also are used by the labs when they are needed. To contact any of ASSET's JTAG DFT Labs to arrange for a free design review, send an e-mail to dftlab@asset-intertech.com or call 888-694-6250 in US or +44 1707 396 056 in Europe.
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InterTech, Inc. |
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