1149.1 BSDL Silicon Validation

1. ScanWorks software syntax and semantics checks are run against the BSDL, to check for IEEE-1149.1 compliance. If needed, power and ground pins are added to the BSDL to ensure proper processing through subsequent test steps.
2. BSDL is compiled into a ScanWorks project, and ATPG test vectors generated for the complete test environment.
3. Compliance-enable pins are set to their static state, prior to the application of power, and the commencement of any testing.
4. The silicon is fixtured to, with the proper power(s) and ground(s) applied to the chip.   TRST, TMS, TCK, TDI and TDO are setup for proper testing.  The tests are run against the silicon first with gated TCK and then with free-running TCK, at a minimum frequency of 1 MHz.
5. A test sequence is generated for the device/BSDL and fixture test environment. The test sequence consists of the following;
1. Reset Action – This merely applies TRST and/or applies a TMS and 5-TCK TAP reset.
2. DR Verify Action – This tests the IDCODE (32 bit register value) and/or BYPASS (1 bit) register for proper code being loaded.  It tests that the Pause DR state can be entered, that a high TMS and 5-TCKs, moves the TAP state machine to Test-Logic-Reset.  It tests an over shift and multiple bit vectors can be loaded into the IDCODE or BYPASS register, and then re-shifted out.  This action validates proper IDCODE and that the TAP signals (TDI, TDO, TMS and TCK) are not stuck at any value.
3. Scan Path Verify Action – This tests similar things to DR Verify, and more! 
1. Device ID and Bypass DR scan Only – This test is almost identical to DR Verify above, except that the TAP controller is NOT forced into the PAUSE_DR state unless in free-running TCK mode.
2. Instruction Capture – This test, tests the hard-coded 01 (per IEEE-1149.1 Spec) that is loaded in the Instruction Register after entering IR Capture state of the TAP state machine.   This also tests the integrity of the Instruction Register TAP state machine path, to ensure proper OP Codes can be loaded into the chip.
3. BYPASS – This test loads the BYPASS instruction into the Instruction Register, and then cycles thru the TAP state machine, to the Shift DR state.  While in Shift DR, it tests the BYPASS Register for the hard coded 0 (per IEEE-1149.1 Spec).  The BYPASS Register is over shifted to ensure it is 1 cell long, and the over shift contains a vector set that ensures a 1 and 0 can be pushed thru the BYPASS Register.
4. IDCODE (if applicable) – Tested on devices that implement the IDCODE instruction. The Instruction Register is loaded with the IDCODE OP Code.  The TAP state machine is then cycled thru SHIFT DR, and the ID CODE (32 bit register) value is tested against the BSDL Code.  If the component does not support the IDCODE instruction, this test uses the BYPASS instruction to check the value captured from the bypass register in the Shift DR state instead.
5. Boundary-Scan Length – This tests to ensure the device under test’s chain length matches the BSDL prior to executing any EXTEST instructions.  Each device is put into SAMPLE, with all other devices put into BYPASS. DR scans are done with a pattern of zeros and ones and a large amount of over shifting. If any mismatch in data is seen, the failure length is reported.
6. USERCODE (if applicable) - test all components implement the USERCODE instruction. This verifies that the devices with user codes match those defined in the BSDL description or configured into the device. This test is only run if a valid USERCODE exists.
7. TRST (if applicable) - Test the proper functioning of the TRST of the devices that implement TRST, one at a time. 
4. Interconnect Action – The Device Under Test (DUT) is Preloaded with data in the serial chain, and taken into EXTEST for full interconnect test.  Each Input, Output and Bi-Directional pin is fully tested for shorts and stuck-at-1 and stuck-at-0 faults.  All applicable drivers are tested, and all applicable receivers are tested.  Bi-Directional pins are tested in both directions for all faults (shorts & stuck-ats).  Directional control cells are tested against their enable and disable state of the BSDL.